A SoC includes an AFE to receive a plurality of differential input channels and generate digitized data corresponding to the channels, and a classification processor configured to receive the digitized data from the AFE. The AFE includes a Dual-Channel Chopper to perform channel multiplexing of two channels while simultaneously chopping the channels, a Dual Channel Charge Recycled-AFE having an Chopper-Stabilized Capacitive-Coupled IA including bias sampling capacitors that store bias values associated with the first and second channels to enable swapping between the channel, and a DC servo loop (DSL) having a reduced setting time based on a reduction in a resistance of the pseudo-PMOS in response to engaging a system reset. The classification processor includes a Frequency-Time Division Multiplexing (FTDM) Feature Extraction (FE) engine and a Dual-Detector Architecture (D2 A) classification processor. The FTDM-FE includes a plurality of FIFOs configured to store, in parallel, the digitized data corresponding to the channels, a plurality of BPF banks storing BPF coefficients, and a single BPF to calculate outputs of one specific bank of the BFP banks for all of the channels. The D2 A processor receives the output from the FTDM-FE and estimates a beginning and end of a seizure using two LSVMs optimized for only sensitivity and specificity, respectively.Dans cette invention, un SoC comprend un AFE destiné à recevoir une pluralité de canaux d'entrée différentielle et à générer des données numérisées correspondant aux canaux, ainsi qu'un processeur de classification conçu pour recevoir les données numérisées en provenance de l'AFE. L'AFE comporte un découpeur bicanal servant à effectuer un multiplexage de deux canaux tout en découpant les canaux, un AFE bicanal à charge recyclée ayant une IA à couplage capacitif stabilisée par découpeur qui possède des condensateurs d'échantillonnage biaisé contenant des valeurs de biais associées aux premier et second canaux pour perme
