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Periodic synchronizer using a reduced timing margin to generate a speculative synchronized output signal that is either validated or recalled
专利权人:
NVIDIA Corporation
发明人:
Dally William J.,Tell Stephen G.
申请号:
US201213688170
公开号:
US9471091(B2)
申请日:
2012.11.28
申请国别(地区):
美国
年份:
2016
代理人:
Zilka-Kotab, PC
摘要:
A method and a system are provided for speculative periodic synchronization. A phase value representing a measured phase of the second clock signal relative to the first clock signal measured at least one cycle earlier is received. A period value representing a period of the second clock signal relative to the first clock signal measured at least one cycle earlier is also received. A reduced timing margin is determined based on the phase value and the period value. A speculatively synchronized output signal is generated based on the reduced timing margin.
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