A programmable logic block for a FPGA comprises two Lookup Tables (LUT) (41, 44). The configuration information for these LUTs (41, 44) is provided by a programmable controller (43), which itself incorporates LUT functionality. This intermediate layer of LUT functionality provides a means to programmatically control the behaviour of the primary LUTs (41, 44) in an operational mode, on the basis of settings made during an initialization mode. Certain embodiments also incorporate a Logic circuit (35), which together with the programmable behaviour of the Primary LUTs provides a means for efficiently implementing a number of common logic functions in including adders, multiplexers, parity and extended LUT and Multiplexer functions. A method for programming an FPGA comprising such a programmable logic block and corresponding data stream are also described.
