The invention relates to a device for resynchronising a plurality of analog signals obtained by conversion using dual data rate (DDR) digital-to-analog converters of a plurality of digital signals having a frequency 2F and synchronised at the output of a digital component. The device includes at least two dual data rate digital-to-analog converters A and B, each converter being respectively connected to an output path of the digital component. The converters A and B receive a same clock signal at a frequency 2F, the converters A and B independently dividing by two said clock signal in order to obtain a clock signal having a frequency F for adjusting their output registers and their input registers to the frequency F. The converter B supplies a clock signal at the frequency F to the digital component in order to adjust the output registers of said component so that the analog signals at the outputs of the converters A and B remain synchronised even if the clock signal at the frequency F obtained by division in
