Logic circuit, processing unit, electronic component, and electronic device

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专利权人:

Semiconductor Energy Laboratory Co., Ltd.

发明人:

Uesugi Wataru,Tamura Hikaru,Isobe Atsuo

申请号：

US201615199004

公开号：

US9704882(B2)

申请日:

2016.06.30

申请国别(地区):

美国

年份:

2017

代理人:

Fish & Richardson P.C.

摘要：

A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

来源网站：

中国工程科技知识中心

来源网址：

http://www.ckcest.cn/home/