Clock Data Recovery Circuitry Associated With Programmable Logic Device Circuitry

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专利权人:

Altera Corporation

发明人:

Aung Edward,Lui Henry,Butler Paul,Turner John,Patel Rakesh,Lee Chong

申请号：

US201615376188

公开号：

US2017155529(A1)

申请日:

2016.12.12

申请国别(地区):

美国

年份:

2017

代理人:

摘要：

A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.

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