A non-volatile memory system includes one or more non-volatile memory cells (20, 40). Each non-volatile memory cell (20, 40) comprises a floating gate, a coupling device (300, 500), a first floating gate transistor (310, 510), and a second floating gate transistor (320, 520). The coupling device (300, 500) is located in a first conductivity region. The first floating gate transistor (310, 510) is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor (320, 520) is located in a third conductivity region. Such non-volatile memory cell (20, 40) further comprises two transistors (330, 340, 530, 540) for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor (320, 520) during an erase operation. The floating gate is shared by the first floating gate transistor (310, 510), the coupling device (300, 500), and the second floating gate transisto
