A logic circuit includes a setting circuit which holds and outputs setting information, a first flip-flop which holds data written to the setting circuit and outputs it in synchronization with an inputted clock, a second flip-flop which holds a write address for selecting the setting circuit and outputs it in synchronization with the inputted clock, and a third flip-flop which holds write enable which allows writing to the setting circuit and outputs it in synchronization with the inputted clock, wherein the setting circuit includes a fourth flip-flop which holds the setting information in synchronization with a given timing signal, and a fifth flip-flop which holds the output of the third flip-flop and outputs a write clock to the fourth flip-flop as the timing signal in synchronization with the inputted clock.
