A signal output board 20 includes: a drive signal generation section 21 configured to generate a drive signal for a CCD 35 an inverse signal generation section 23 configured to generate an inverse signal by inverting a phase of the drive signal from the drive signal generation section 21 a first signal transmission line portion 24 configured to transmit the drive signal from the drive signal generation section 21 a second signal transmission line portion 25 configured to transmit the inverse signal from the inverse signal generation section 23, at least part of the second signal transmission line portion being arranged in parallel to and adjacent to the first signal transmission line portion 24 and an output end portion 26 configured to output the drive signal transmitted by the first signal transmission line portion 24, to the outside.
