ON-THE-FLY TEST AND DEBUG LOGIC FOR ATPG FAILURES OF DESIGNS USING ON-CHIP CLOCKING

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专利权人:

STMicroelectronics International N.V.

发明人:

Syed Danish Hasan

申请号：

US201615284070

公开号：

US2017023647(A1)

申请日:

2016.10.03

申请国别(地区):

美国

年份:

2017

代理人:

摘要：

A system disclosed herein includes an on-chip clock controller (OCC) circuit receiving a test pattern and responsively generating output clock pulses in response to the test pattern. An OCC test circuit is coupled to the OCC circuit and configured to detect data corresponding to output clock pulses generated by the OCC controller circuit and generate corresponding OCC test outputs. A test output logic circuit is configured to receive the OCC test outputs from the OCC test circuit. A debug controller is operable to configure the test output logic circuit to output the OCC test outputs.

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中国工程科技知识中心

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http://www.ckcest.cn/home/