Bell, Jr. Robert H.,Chiang Men-Chow,Hua Hong L.,Srinivas Mysore S.
申请号：
US201213633893
公开号：
US9626294(B2)
申请日:
2012.10.03
申请国别(地区):
美国
年份:
2017
代理人:
Baudino James L.
摘要：
According to one aspect of the present disclosure a system and technique for performance-driven cache line memory access is disclosed. The system includes: a processor, a cache hierarchy coupled to the processor, and a memory coupled to the cache hierarchy. The system also includes logic executable to, responsive to receiving, a request for a cache line: divide the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; service the high priority data request; and delay servicing of the low priority data request until a low priority condition has been satisfied.
