This document discusses, among other things, a communication circuit for an IMD comprising a radio frequency (RF) modulator to modulate and demodulate IMD data signals, first and second serial buffer registers to store received demodulated data and to store transmit data for modulation and configured to operate according to a first clock signal, and a parallel buffer register to receive data in parallel from the first and second serial buffer registers and configured to operate according to a second clock signal that is slower than the first clock signal. The communication circuit also includes a telemetry control circuit configured to, when in the receive mode, alternate between serially receiving data into the first serial buffer register while the parallel buffer receives data from the second serial buffer register, and serially receiving data into the second serial buffer register while the parallel buffer receives data from the first serial buffer.
