A signal processing device 6 includes a first internal module 61 that executes hardware processing, and second internal modules 62 and 63 that execute software processing. The first internal module 61 outputs an image signal, division position information indicating division positions, at which a frame of the image signal is divided by a predetermined amount of data, and a timing signal, to the second internal modules 62 and 63, and generates, based on the image signal that has been subjected to the software processing and input from the second internal modules 62 and 63, a video signal for display. Based on the timing signal and the division position information, the second internal modules 62 and 63 sequentially execute image processing by the software processing on the image signal per the predetermined amount of data, and sequentially output the image signal per the predetermined amount of data that has been subjected to the image processing, to the first internal module 61.
