A peripheral controller, and method of operation, for half duplex communication between a system and a peripheral, in which a system clock and a peripheral clock are asynchronous, are described. A FIFO includes a FIFO controller and a FIFO memory and has a plurality of inputs. A multiplexer circuit is connected to the plurality of inputs, and is operable by a selection signal to supply either a first group of system and peripheral signals or a second group of system and peripheral signals to the FIFO to operate the FIFO to transmit data from the system to the peripheral or to receive data at the system from the peripheral.
