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Apparatus and method for detecting postures using Force Sensing Resistor sensor
专利权人:
동서대학교산학협력단;(주)와이제이솔루션
发明人:
김현우,노윤홍,박준모,정도운
申请号:
KR1020150021875
公开号:
KR1016760260000B1
申请日:
2015.02.12
申请国别(地区):
KR
年份:
2016
代理人:
摘要:
The present invention relates to an apparatus and method for detecting an orientation using an FSR sensor. A first aspect of the present invention is a method for detecting a force of a force sensing device, the force sensing device comprising: a force sensing resistor (FSR A) 11 a; a force sensing resistor B 11 b; a force sensing resistor C 11 c; ), A first amplifier 12a, a second amplifier 12b, a first Schmitt trigger circuit 13a, and a second Schmitt trigger circuit 13b. The output signals of the FSR A 11a and the FSR C 11c are input to the input terminal of the OR gate 14 via the first amplifier 12a and the first Schmitt trigger circuit 13a The output signals of the FSR B 11b and the FSR D 11d are inputted to the input terminal of the OR gate 14 through the second amplifier 12b and the second Schmitt trigger circuit 13b And an attitude detecting device using the FSR sensor. In the second aspect of the present invention, the FSR A (11a) arranged in the front, the FSR C (11c) arranged in the rear, the FSR B (11b) arranged in the left, (Front) and rear (rear) of the front (front), rear (rear), left and right voltage balance signals respectively output from the FSR D 11d are amplified by the first amplifier 12a, And the second amplifier 12b amplifies and outputs the amplified signal on the right side; The first Schmitt trigger circuit 13a receives the output signal obtained by amplifying the voltage balance signals of the front (front) and rear (rear) from the first amplifier 12a and the left and right voltages A second step in which the second Schmitt trigger circuit 13b receives an output signal obtained by amplifying the balance signal; The first and second Schmitt trigger circuits 13a and 13b output FSR A 11a, FSR B 11b, FSR C 11c and FSR D 11d, A third step of outputting a high signal or a low signal to the first switch; And the OR gate 14 receive the four output signals of the third stage as input signals and when all the input signals are low signals, a low s
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