The invention relates to a variable capacitor circuit (100) comprising a plurality of MOS capacitors (110), each MOS capacitor being implemented by a MOS transistor with the gate terminal connected to a first voltage signal (Vs) and with the drain terminal shorted with the source terminal and connected to a second voltage signal (Vc), said MOS capacitors being connected in parallel through the gate terminal connected to the first voltage signal (Vs), and being operated in a cut-off region (120) in which the equivalent capacitance (C) of each MOS capacitor remains substantially constant for variations of the first voltage signal. The invention also relates to a method for compensating a capacitance mismatch in a biomedical signal acquisition system using the described variable capacitor circuit (100).
