An input signal is segmented by a first data latch into 2 bit segments according to rising and falling edges of a clock signal clk, and latched. When the input signal is an RSDS signal, 2 sets worth of 2 bit data are latched according to rising and falling edges of a clock signal clkx2, using a first output section, a first data holding section, and a second output section. When the input signal is a mini-LVDS signal, 4 clock cycles worth of data are held according to the rising and falling edges of the clock signal clkx2 using the first data holding section and the second output section. One set's worth of 8 bit data is then latched according to a rising edge of a clock signal clkx4 using the first output section, a third output section, a fourth output section, and a fifth output section.
