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受信回路および通信回路
专利权人:
富士通株式会社
发明人:
土肥 義康
申请号:
JP20130062723
公开号:
JP6127635(B2)
申请日:
2013.03.25
申请国别(地区):
日本
年份:
2017
代理人:
摘要:
A receiving circuit includes: an interpolation circuit that generates, by using an interpolation coefficient, output data including a data point and a boundary point from pieces of input data that are input in chronological order; a detection circuit that outputs a detection signal when the detection circuit detects a phase of the output data by using the boundary point of the output data; a low pass filter that filters the detection signal and generates the interpolation coefficient; and a modulation circuit that modulates, by using a modulation signal having a frequency different from a cutoff frequency of the low pass filter, the interpolation coefficient generated by the low pass filter, and outputs the modulated interpolation coefficient to the interpolation circuit.
来源网站:
中国工程科技知识中心
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http://www.ckcest.cn/home/

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