A processor 3 includes: a data transmission/reception section 26 that reads parameter data unique to a scope 2 from a ROM 12 provided in the scope 2 a register communication state determination section 24 that determines whether or not the parameter data read from the data transmission/reception section 26 has an error and a mute control/color bar control section 25 that if a result of the determination by the register communication state determination section 24 indicates that the parameter data has an error, controls an image processing section 21 according to a type of the parameter data having the error.