KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
发明人:
CHO, GYU SEONG,조규성,CHO, MIN SIK,조민식,KIM, HYUNG TAEK,김형택,CHO, GYU SEONGKR,CHO, MIN SIKKR,KIM, HYUNG TAEKKR
申请号：
KR1020160046978
公开号：
KR1017176870000B1
申请日:
2016.04.18
申请国别(地区):
KR
年份:
2017
代理人:
摘要：
The present invention provides a driving circuit having a function of selecting only an effective signal by using a digital logic within a circuit. The present invention comprises: a first OR gate configured to output a fourth signal obtained by OR operation of a first delay signal and a second delay signal； a second D flip flop receives a fifth signal outputted by inputting the fourth signal and a third signal to a second OR gate； and an AND gate configured to output a timing signal.본 발명에서는 회로 내의 디지털 로직을 이용하여 유효한 신호만을 선별하는 기능을 갖는 구동회로장치를 제공한다.
