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制御信号生成回路及び回路装置
专利权人:
株式会社オートネットワーク技術研究所;住友電装株式会社;住友電気工業株式会社
发明人:
佐藤 慎一郎,高井 伸彰
申请号:
JP20130246525
公开号:
JP6277691(B2)
申请日:
2013.11.28
申请国别(地区):
日本
年份:
2018
代理人:
摘要:
PROBLEM TO BE SOLVED: To provide a control signal generation circuit and a circuit device that can suppress a deterioration in controllability of a high side switch and a low side switch caused by providing a dead time.SOLUTION: In a control signal generation circuit 1, a first delay circuit 11 outputs a delayed and logically inverted version of an input pulse signal. The first delay circuit 11 does not change a duty ratio of the input pulse signal. A signal inverted in a logical inversion element J21 from the output signal of the first delay circuit 11 is output as a high side control signal. A second delay circuit 12 outputs a delayed rise version of the output signal of the first delay circuit 11. A signal inverted in a logical inversion element J24 from the input pulse signal and a signal shaped in logical inversion elements J22 and J23 from the output signal of the second delay circuit 12 are input into an OR element A1, and an OR signal of both the signals is output as a low side control signal.
来源网站:
中国工程科技知识中心
来源网址:
http://www.ckcest.cn/home/

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