An interface module 61 relays control signal communication between a main CPU 621 and a light source control CPU 651 and between the main CPU 621 and a camera head CPU 242. The interface module 61 includes an FPGA 610 having CPU I/Fs 611 to 613 that correspond to communication schemes of CPUs 621, 651, and 242, respectively, and first and second storage units 615 (617) and 616 (618). The FPGA 610 relays a control signal between the main CPU 621 and the light source control CPU 651 and between the main CPU 621 and the camera head CPU 242, while temporarily storing the control signal in the first and the second storage units 615 (617) and 616 (618). Moreover, a first communication timing and second and third communication timings are set at timings shifted from one another.
