Emanuel Feldman,Jordi Parramon,Paul J. Griffith,Jess Shi,Robert Tong,Goran Marnfeldt
申请号：
US16443609
公开号：
US20190299007A1
申请日:
2019.06.17
申请国别(地区):
US
年份:
2019
代理人:
摘要：
A new architecture is disclosed for an IPG having a master and slave electrode driver integrated circuits (ICs). The electrode outputs on the ICs are wired together. Each IC can be programmed to provide pulses with different frequencies. Active timing channels in master and slave ICs are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other IC so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.
